Hardware and Environment Setup

Hardware Requirements

Development Board

The following Intel FPGA platforms are tested with XploR Studio IDE:

  • Intel FPGA DE2-115 development board

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  • Intel Stratix 10 GX board

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USB RS232 adapter

The following USB-RS232 adapters are tested:

  • UGreen USB-RS232 adapter

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USB Ethernet adapter (optional)

The following USB-Ethernet adapters are tested:

  • UGreen USB Ethernet adapter

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Intel DE2-115 Board

The connection between the PC and the Intel DE2-115 board is shown in the below diagram:

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We use a single JTAG cable to flash an FPGA board and debug RISC-V IP via Virtual JTAG (vJTAG) to make things easier for the user. So please disconnect the unused FPGA board when using vJTAG.

Connection for Embedded Linux projects

The connection between the PC and the Intel Stratix 10 GX board is shown in the below diagram:

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Connection for FreeRTOS and Embedded projects

Intel Stratix 10GX board

  • Disable Max V on JTAG chain for Stratix 10 GX

  • Locate SW6 JTAG Bypass DIP switch

  • Change SW6-2 to ON in order to bypass MAX V (The default position is OFF)

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FMC XM105 Debug Card is plugged into Intel FPGA Stratix 10 GX board

UART connection

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SignalUART AdapterFMC XM105 Debug CardStratix 10 GX
UART0RXDJ16 pin #9 - TXDAV13
TXD (GREEN)J16 Pin #7 - RXDBC11
UART1RXDJ16 pin #12 - TXDAY13
TXD (GREEN)J16 Pin #10 - RDXAW13
Other pinsNONO

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JTAG connection

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Altera USB blaster

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USB Bus blaster

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SignalBus blaster JTAG Debugger v3FMC XM105 Debug Card
TRSTTRSTJ20 pin #1
TDITDIJ20 pin #4
TDOTDOJ20 pin #7
TMSTMSJ20 pin #3
TCKTCKJ20 pin #8
GNDGNDJ5 pin #2
VREFVREFJ15 pin #1

ARM Olimex

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Driver installation

On Windows

To recognize the USB blaster, drivers are needed to be installed.

  1. Open the Device Manager (Control Panel | Device Manager).

  2. Right-click on the USB Blaster and then select Update driver ….

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  1. Select Browse my computer for driver software.

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  1. Select Browse… to select the driver you downloaded and extracted above, then click Next to install the driver.

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  1. After that, the driver should have been successfully installed.

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If you see that the Altera USB Blaster II is unconfigured

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and when flashing, the board cannot be detected; open Quartus programmer with administrator rights, wait a few seconds for Quartus Programmer to update the settings.

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After the settings are updated, the JTAG USB can be used.

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On Linux

On Ubuntu 20.04 desktop, drivers are available. The installer will add rules to udev configuration to use devices. User can check the added rules in the file /etc/udev/rules.d/51-usbblaster.rules

# USB-Blaster
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6001", MODE="0666", GROUP="plugdev"
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6002", MODE="0666", GROUP="plugdev"
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6003", MODE="0666", GROUP="plugdev"

# USB-Blaster II
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6010", MODE="0666", GROUP="plugdev"
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6810", MODE="0666", GROUP="plugdev"

Unplug and plug USB cables.

Service installation

This part is only needed for setting up an environment for debugging RISC-V Embedded Linux Project. If you are interested in embedded and FreeRTOS applications only, please skip this part.

Network setup

The current built-in SoC SOFs for DE2-115 support 10 Mbps (MII mode) and 1000 Mbps (RGMII mode) Ethernet network. Depending on your network setup, please use the correct SOF file when programming the DE2-115 board.

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To debug embedded Linux RISC-V applications on the board, the following requirements are mandatory for the connection between the host PC and the DE2-115 board.

RGMII mode:

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  • Network interface on the host PC connects to ETHERNET0 of DE2-115. The connection could be directly or via router/switches.
  • On the board, set Jumper JP1 to pins 1 and 2. It’s default mode (RGMII mode).
  • Default IP addresses:
    • DE2-115 board:
    • TFTP server:

On the PC, the IP address is set to If users want to use a different subnet, please update the IP of the board. To update the IP of the board, after flashing FPGA bitstream, open the /dev/ttyUSB* or COM* port console to the board and set the IP as:

eth_local_ipSet the IP address of the board
eth_remote_ipSet the expected IP of the TFTP Server to download kernel/rootfs for network booting
netbootStart booting Linux from the network

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MII mode:

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  • Network interface on the host PC connects to port 0 of DE2-115.
  • Connection speed is 10 Mpbs.
  • On the board, set Jumper JP1 to pins 2 and 3 (to config Ethernet port 0 to run on MII mode).
  • On the PC, the IP address is set to The network speed and IP can be set with the following command:
# Assume that the network interface is enxf8e43b5dd64a
sudo ethtool -s $NIC speed 10 duplex full autoneg off
# Double check
ethtool $NIC
# IP needs to be fixed as
# Make sure that IPv4 method is manual
sudo ifconfig $NIC

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TFTP server

To debug embedded Linux applications, a TFTP server needs to be set up on the development PC to host Linux /images_hardware. This Linux image will be loaded when the board is flashed.

TFTP server on Linux

The quickest way to set up a TFTP server is using docker as follows:

  • Create tftpboot directory
  • Copy boot.bin to tftpboot directory
  • Start the TFTP server
docker rm -f tftpboot
cd tftpboot
# Copy boot.bin (here)
docker run -itd --name=tftpboot --net=host  --restart=always -v ${PWD}:/var/tftpboot  pghalliday/tftp

SolarTFTP server on Windows 10


  • Administrator permission

  • SolarWinds TFTP Server: To set up a TFTP server, users will have to download the TFTP Server utility such as SolarWinds can be downloaded from https://www.solarwinds.com/free-tools/free-tftp-server. Once the .zip file is downloaded, extract it and go through the straightforward installation.

  • Firewall setup: To allow remote access to the TFTP server, users need to open the firewall for TFTP service.

Start the TFTP Server

Run the SolarWinds TFTP Server utility by going to the Start Menu and searching for TFTP Server.

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Once it loads up, copy the boot.bin (RISC-V Linux image) to C:\TFTP-Root folder.