Litex C HelloWorld

This chapter covers the basics of C embedded projects including creating, building, running, and debugging embedded applications. The project referred to in this chapter is called “Hello World.” This application prints “Hello World” text and runs a simple for-loop as a simple demonstration. The application can also be built and run on FPGA.

Note: To build, run and debug Embedded applications with FPGA, there are some blueprints that need to be installed first:

• xplor-studio-elf: XploR plugin for creating baremetal project

• xplor-studio-openocd: Xplor plugin for debugging with hardware

• baremetal-neorv32-de2115: The baremetal example of NEORV32 core on Terrasic DE2-115 board

  

Please refer to Guidelines for more information.

Create a new project

Select File > New > C Project choose RISC-V Embedded Project > RISC-V Helloworld (NEORV32) project and Toolchains: Baremetal XploR Toolchain for RISC-V then click Next.

Then click Next.

Then click Finish.

Update build settings

The build setting is the same as the quick-start project’s settings. Please refer to Update build settings for more information.

Build project

The build step is the same as the quick-start project’s step. Please refer to Build project for more information.

Running and Debugging project with Intel FPGA DE2-115 platform

Hardware and driver preparations

Please refer to the Hardware and Environment Setup document for more details.

Programming IP core

To program a RISC-V IP core to the board, click on Flash icon on the toolbar

• In the IP Core, select de2115-neorv32.sof or Custom IP core if users use their own RISC-V IP core. In this case, we select de2-115_neorv32 for the neorv32 - DE2-115 project.
• Select JTAG cable (if the user has multiple boards connected to the development machine).
• Click Finish to flash Neorv 32-bit RISC-V core to DE2-115 board.

To view the console output printed from the RISC-V core, open the Terminal view and select COM port (on Windows) or /dev/ttyUSBx port (on Linux) with the following connection settings.

The output message on the serial terminal will look like this:

    _   _           _           ____         ____ 
   | | | |_   _  __| |_ __ __ _/ ___|  ___  / ___|
   | |_| | | | |/ _` | '__/ _` \___ \ / _ \| |    
   |  _  | |_| | (_| | | | (_| |___) | (_) | |___ 
   |_| |_|\__, |\__,_|_|  \__,_|____/ \___/ \____|
          |___/                                   

           Maximize your SoC design!

 (c) Copyright 2020-2023 SoC.One
 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS CRC passed (42b17cce)

 HydraCore git sha1: --------

--=============== SoC ==================--
CPU:            NEORV32 @ 50MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            64.0KiB
SRAM:           64.0KiB
SDRAM:          128.0MiB 32-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM:       128.0MiB

--========== Initialization ============--
Ethernet init...
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB     
   Read: 0x40000000-0x40200000 2.0MiB     
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 14.4MiB/s
   Read speed: 11.7MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
             Timeout
Booting from network...
Local IP: 192.168.1.50
Remote IP: 192.168.1.100
Booting from boot.json...
Booting from boot.bin...
Copying boot.bin to 0x40000000... 
Network boot failed.
No boot medium found

--============= Console ================--

litex> 

Run project on Terrasic FPGA DE2-115 platform

It is recommended to program the bitstream to Intel FPGA board before starting project debugging. Please refer to previous section for how to program the bitstream.

To run the application on hardware without debugging, select project in the Project Explorer, click Run as > Run configurations.

Then create a new RISC-V Running configuration with the following information.

• Platform: FPGA > Terrasic Board > Neorv32

On the Terminal view, the message will be printed.

Both Neorv32 and Rocket Chip on DE2-115 board use Virtual JTAG to run/debug.

Debug project on Terrasic FPGA DE2-115 platform

It is recommended to program the bitstream to Intel FPGA board before starting project debugging. Please refer to previous section for how to program the bitstream.

To debug the application on hardware, select project in the Project Explorer, click Debug as > Debug Confihurations

Then create a new RISC-V Running configuration with the following information. On tab Debugger:

• Platform: FPGA > Terrasic DE2-115 Board > Neorv32

After selecting Apply and Debug, the IDE changes to the debug perspective and automatically sets a breakpoint in the first line of code in the main() function.

Other functions of debugging (such as Resume, Step Into, Step Over, Step Return, Terminate, …) are the same as the common project’s. Please refer to Running and Debugging project with QEMU emulator for more information.

Both Neorv32 and Rocket Chip on DE2-115 board use Virtual JTAG to run/debug.

Debug project with custom openocd

Create a new debug configuration on Debug Configurations dialog by double-clicking on RISC-V Debugging:

On the tab Debugger, select option Terrasic DE2-115 Board in FPGA

On the OpenOCD Options, we use the openocd binary of Quartus and the default openocd configuration file.

Users can browse the custom openocd binary and the custom openocd configuration file.

Click Apply then click Debug to start debugging with the custom openocd binary.