Execution platforms

With the advent of open source CPU implementation (e.g. openRISC ), and open ISA (e.g. RISC-V), opportunities exist for developers to innovate on both side of the coin: in both hardware and software (i.e. software-hardware co-design and development)

To properly supports software-hardware co-design for pre-silicon development, the embedded target must be able to host different hardware designs consisting of different ISA implementation (and sometimes more than one), HW IP(s) and peripherals, and on-chip topology.

Target execution platform(s) are platform devices with circuits that can be manipulated with hardware description language (HDL) to perform specific functions, including those of a microprocessor or a complete system on chip (SoC).

Examples: FPGA(s) are common target execution platforms used for prototyping and deployment. Emulators and arguably cycle-approximate instruction set simulators, used for verification and early software development, are other examples.

In the context of pre-silicon development, programming means:

• The manipulation of the device circuits with specific HDL (hardware programming, or flashing), or
• The loading and debugging of executable code and data (software programming, or loading) into the memory of the microprocessor that is executing on the target execution platform.

XploR Studio supports both mode of programming support both pre and post silicon software development.

Virtual JTAG: Many XploR components for execution platforms include builtin virtual JTAG supporting hardware and software programming, thus obviating the needs for costly and less convenient external JTAG device from third-parties.

mainframe Target execution platform as the embedded target

state "Host Development System" as hosts 
hosts : Linux or Windows on x86 / ia64

state "Pre-silicon target execution platform" as targets {
  state JTAG
  state "HDL programmable device" as HAPS {
    state CPU : x86 or ARM
    state Memory : DDR, SRAM, ...
    state Peripherals : USB, Ethernet, ...
  }
  JTAG --> HAPS
}
note bottom of HAPS : CPU, Memory and Peripherals\nare (or can be) programmed with HDL.
state JTAG
note top of JTAG : JTAG used for both hardware\nand software programming

hosts -> JTAG